Computing with Invertible Logic: Combinatorial Optimization with Probabilistic Bits

Special purpose accelerators for solving combinato-rial optimization problems have been receiving increasing attention. One contender in this approach is based on probabilistic computing with probabilistic or p-bits. P-bits constitute the fundamental computational unit between bits and q-bits, fluc-Tuating between logic 0 and 1. Modified magnetoresistive RAM technology opens up the possibility of building highly integrated probabilistic computers with millions of p-bits. For medium-scale p-bit based accelerators conventional CMOS technology using FPGAs and ASICs offer a competitive alternative. Here, we present some of the latest results using p-bits, in sparse, modular, and scalable p-circuits. Results are presented for combinatorial optimization problems such as integer factorization and Boolean satisfiability (SAT), using the principles of invertible logic for generating hardware-Aware graph representations. Invertible logic allows the design of Boolean circuits that can be operated in reverse: for example, a digital multiplier built out of elemental logic gates (AND, OR, NOT), can be used to factor integers. Similarly, SAT problems can simply be solved by constructing the corresponding logical circuit in hardware and running it in re-verse. Using powerful probabilistic algorithms such as simulated annealing and parallel tempering, we show how interconnected p-bits in invertible probabilistic circuits can solve computationally hard optimization problems such as Boolean SAT and integer factorization up to 25-bit semiprimes (in the tens of millions) showing competitive performance amongst all Ising Machines.