A Simplified Topology for the Design of Low Noise Voltage Amplifiers for Low Frequency Noise Measurements

We propose a simple topology for the design of very low noise voltage amplifiers dedicated to low frequency noise measurement applications. The topology is based on a low noise discrete JFET first stage, that acts as a buffer providing for negligible equivalent input current noise, followed by a very low noise BJT input instrumentation amplifier. Excellent noise performances in the low frequency range (f < 10 Hz) can be obtained notwithstanding the very low component count enabling simple construction. As an example, when using just one of the two large area, low noise JFETs in the IF3602 differential pair as the input device, the equivalent input voltage noise can be as low as 16 nV}/√Hz at 100 mHz, 3.5nV/√Hz at 1 Hz and below 1.4 nV/√ Hz for frequencies above 20 Hz. Depending on the application at hand, the input stage design can be easily modified using different JFETs (or combination of JFETs) in order to obtain different compromises in terms of background noise, lower frequency limit, settling time and equivalent input capacitance.