The second ALICE Inner Tracking System upgrade project (ITS3), to be completed during LHC Long Shutdown 3 (LS3, 2026-2028), will dramatically reduce the Inner Barrel (IB) detectors’ material budget and thus improve the ITS tracking capabilities (detection efficiency and track resolution). For this purpose, the ITS3 project envisions replacing the current ITS2 IB with 6 flexible, truly cylindrical half-layers, supported only by a carbon foam frame and cooled down by an air system. The ITS3 will be made of CMOS Monolithic Active Pixel Sensors (MAPS) produced with a 65 nm technology. This innovative project has required a remarkable effort in terms of R&D, going from the design to the testing of small devices. In this contribution studies on the first small test device submission (MLR1) will be presented. Those studies have been carried out with the goal to compare different silicon chip manufacturing processes, doping profiles, front-end configurations, and generally validate 65 nm technology for the ITS3 CMOS MAPS.

MLR1: CMOS MAPS technology validation for ALICE ITS3

Sturniolo, Alessandro
2025-01-01

Abstract

The second ALICE Inner Tracking System upgrade project (ITS3), to be completed during LHC Long Shutdown 3 (LS3, 2026-2028), will dramatically reduce the Inner Barrel (IB) detectors’ material budget and thus improve the ITS tracking capabilities (detection efficiency and track resolution). For this purpose, the ITS3 project envisions replacing the current ITS2 IB with 6 flexible, truly cylindrical half-layers, supported only by a carbon foam frame and cooled down by an air system. The ITS3 will be made of CMOS Monolithic Active Pixel Sensors (MAPS) produced with a 65 nm technology. This innovative project has required a remarkable effort in terms of R&D, going from the design to the testing of small devices. In this contribution studies on the first small test device submission (MLR1) will be presented. Those studies have been carried out with the goal to compare different silicon chip manufacturing processes, doping profiles, front-end configurations, and generally validate 65 nm technology for the ITS3 CMOS MAPS.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11570/3341812
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