Silicon carbide is a wide-band gap semiconductor material which became the most desirable candidate for automotive applications making power transistors with high power density module featuring high blocking voltage and ultra-low conduction resistance due to its better physical properties than silicon such as a wider bandgap of around 3eV, an about ten times higher critical electric field and an about three times higher thermal conductivity. These features allow higher operation temperature, better efficiency in power conversion, power rate and switching frequency which, combined with very fast process improvement, contributed to make it technologically mature as commercial products. Unfortunately, the gate oxide weakness, the presence of carbon atoms in the crystal which results in a slow oxide growth rate and the high amount of crystal defects in SiC wafers are currently cutting back the total exploitation of all these performances. As deepen explained on chapters related to defectivity cap. 5, for the next generation of SiC based power devices improvement of quality and technical parameters of devices requires better control of material during the epitaxial growth. On that phase, crystallographic defects and contaminations may extend into epitaxial layer and wafer surface to form various surface defects, including carrot defects, polytype inclusions, scratches, micropipes, dislocations and grain boundaries, or even convert to produce other defects, leading to detrimental effects on the final SiC device such as critical breakdown electric field reduction, higher leakage currents, and degrade the on-state performance of devices. Defects such that are then considered to be device-killer since they kill or severely damage the electrical properties of the devices, hence they need to be appropriately characterized and deepen studies on their effect on reliability are needed. Other non-killer defects such as basal plane dislocations and threading edge dislocations might not kill the electrical properties of the devices but can cause performance degradation and excessive defect induced leakage current. Usually, they could be activated under transistor on conditions which are related to positive bias on gate electrode. Moreover, efforts have recently been intensified to characterize the gate oxides also in a condition of negative polarization due to the negative electric field induced, as shown in several simulations, on the gate oxide in a condition of high drain polarization. On the other hand, in the field of batteries application, negative bias characterization has been required to characterize the accidental case of reversing electrodes polarity. These are the reasons why, during the past decades, extensive studies have been conducted to understand the impact of major SiC defects, to reduce their amount and to address correctly and efficiently failure analysis related to them. The starting point obviously, requires a fully and accurate characterization of the most reliability test implemented on standard and defect free devices to understand the normal aging of the transistor under accelerated test. In this context, the 4H-SiC MOSFETs bias temperature instability during long term interdiction including high temperature reverse bias and high temperature gate bias are the routinely performed. Which is done to ensure the reliability aspect of the devices operating in high temperature and voltage to accelerate degradation induced by latent extended or point defectivity, which are not detected at parametric and functionality test. The purpose of each test is, for the former to check the integrity of the junction, the weakness due to crystal defectivity in the field depletion structure, known as JFET area, or at the edge termination and for the latter the drift of electrical parameters related to charge trapping at SiC/SiO2 interface, bulk oxide traps in the gate oxide. The main issue in failure analysis is often the addressing after an irreparable damage to the structure which is the usual output of a standard reliability test such as HTRB and HTGB. The results will confirm how defectivity is detrimental to device reliability under HTRB test inducing sudden breakdown which, according to the simulation are located at device edge although In-depth studies are still underway to understand whether some types of extended defects are sensitive to charge trapping and therefore induce parametric drift during stress before hard failure. Therefore, the main topics of this work: 1. Perform the numerical simulation to obtain information about the equivalence, in terms of electric field, between a negative HTGB and a HTRB stress 2. Provide a graphical distribution of the electric field and the most critical points into the device cross section suggesting the worst-case stress under different polarities 3. Test and measurement’s purpose to confirm on several “defect-free” devices the hypothesis deduced by simulation monitoring the real aging and parameter drifting under stress 4. Test several defected devices to understand if the extended defects are electrically active and/or also if they include contamination and energy levels in the band gap being subjected to progressive degradation or, otherwise, being not related to point defects, to a sudden breakdown 5. Carry out the electrical characterization of the defect a Raman Spectroscopy on a most common defect on 4H-SiC epitaxy

Defect Characterization and Reliability effect on 4H-SiC PowerMOSFET

ANOLDO, Laura
2023-11-24

Abstract

Silicon carbide is a wide-band gap semiconductor material which became the most desirable candidate for automotive applications making power transistors with high power density module featuring high blocking voltage and ultra-low conduction resistance due to its better physical properties than silicon such as a wider bandgap of around 3eV, an about ten times higher critical electric field and an about three times higher thermal conductivity. These features allow higher operation temperature, better efficiency in power conversion, power rate and switching frequency which, combined with very fast process improvement, contributed to make it technologically mature as commercial products. Unfortunately, the gate oxide weakness, the presence of carbon atoms in the crystal which results in a slow oxide growth rate and the high amount of crystal defects in SiC wafers are currently cutting back the total exploitation of all these performances. As deepen explained on chapters related to defectivity cap. 5, for the next generation of SiC based power devices improvement of quality and technical parameters of devices requires better control of material during the epitaxial growth. On that phase, crystallographic defects and contaminations may extend into epitaxial layer and wafer surface to form various surface defects, including carrot defects, polytype inclusions, scratches, micropipes, dislocations and grain boundaries, or even convert to produce other defects, leading to detrimental effects on the final SiC device such as critical breakdown electric field reduction, higher leakage currents, and degrade the on-state performance of devices. Defects such that are then considered to be device-killer since they kill or severely damage the electrical properties of the devices, hence they need to be appropriately characterized and deepen studies on their effect on reliability are needed. Other non-killer defects such as basal plane dislocations and threading edge dislocations might not kill the electrical properties of the devices but can cause performance degradation and excessive defect induced leakage current. Usually, they could be activated under transistor on conditions which are related to positive bias on gate electrode. Moreover, efforts have recently been intensified to characterize the gate oxides also in a condition of negative polarization due to the negative electric field induced, as shown in several simulations, on the gate oxide in a condition of high drain polarization. On the other hand, in the field of batteries application, negative bias characterization has been required to characterize the accidental case of reversing electrodes polarity. These are the reasons why, during the past decades, extensive studies have been conducted to understand the impact of major SiC defects, to reduce their amount and to address correctly and efficiently failure analysis related to them. The starting point obviously, requires a fully and accurate characterization of the most reliability test implemented on standard and defect free devices to understand the normal aging of the transistor under accelerated test. In this context, the 4H-SiC MOSFETs bias temperature instability during long term interdiction including high temperature reverse bias and high temperature gate bias are the routinely performed. Which is done to ensure the reliability aspect of the devices operating in high temperature and voltage to accelerate degradation induced by latent extended or point defectivity, which are not detected at parametric and functionality test. The purpose of each test is, for the former to check the integrity of the junction, the weakness due to crystal defectivity in the field depletion structure, known as JFET area, or at the edge termination and for the latter the drift of electrical parameters related to charge trapping at SiC/SiO2 interface, bulk oxide traps in the gate oxide. The main issue in failure analysis is often the addressing after an irreparable damage to the structure which is the usual output of a standard reliability test such as HTRB and HTGB. The results will confirm how defectivity is detrimental to device reliability under HTRB test inducing sudden breakdown which, according to the simulation are located at device edge although In-depth studies are still underway to understand whether some types of extended defects are sensitive to charge trapping and therefore induce parametric drift during stress before hard failure. Therefore, the main topics of this work: 1. Perform the numerical simulation to obtain information about the equivalence, in terms of electric field, between a negative HTGB and a HTRB stress 2. Provide a graphical distribution of the electric field and the most critical points into the device cross section suggesting the worst-case stress under different polarities 3. Test and measurement’s purpose to confirm on several “defect-free” devices the hypothesis deduced by simulation monitoring the real aging and parameter drifting under stress 4. Test several defected devices to understand if the extended defects are electrically active and/or also if they include contamination and energy levels in the band gap being subjected to progressive degradation or, otherwise, being not related to point defects, to a sudden breakdown 5. Carry out the electrical characterization of the defect a Raman Spectroscopy on a most common defect on 4H-SiC epitaxy
SiC, Silicon Carbide, PowerMOSFET, Reliability, Semiconductors
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11570/3244823
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