In this article, a scalable subterahertz equivalent circuit model for complementary metal–oxide–semiconductor (CMOS) transistors is proposed. At subterahertz frequencies, signal propagation exhibits extremely rapid dynamics, causing the nonquasi-static (NQS) effect to become pronounced. To address this challenge, a dispersive nonlinear resistance model based on carrier transport mechanisms was developed. This model integrated both carrier drift and diffusion effects, and further characterized the frequency dispersion phenomena associated with the NQS effect. Concurrently, a scalable gate capacitance model was established from the perspective of channel charge distribution. In addition, the scaling rules of parasitic parameters in the equivalent circuit model were presented. For model validation, 12 CMOS transistors with varying geometries were designed and fabricated in a partially depleted silicon-on-insulator (PDSOI) process. Subsequently, ultrawideband scattering (S -) parameter measurements were performed on these devices across the frequency range from 0.2 to 320 GHz. By comparing the model calculation results with the measured data, the maximum root-mean-square error of the model was 0.074. Furthermore, the proposed model was verified to have scaling capability across three geometric dimensions: gate length (L), single-finger gate width (Wf), and the number of gate fingers (Nf). This scalable model provides accurate modeling support for high-frequency circuit design.
A 320-GHz Scalable Equivalent-Circuit Model With Dispersive NQS Effect for CMOS Transistors: From Theory to Experimental Validation
Gugliandolo G.;Donato N.;Crupi G.Penultimo
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2026-01-01
Abstract
In this article, a scalable subterahertz equivalent circuit model for complementary metal–oxide–semiconductor (CMOS) transistors is proposed. At subterahertz frequencies, signal propagation exhibits extremely rapid dynamics, causing the nonquasi-static (NQS) effect to become pronounced. To address this challenge, a dispersive nonlinear resistance model based on carrier transport mechanisms was developed. This model integrated both carrier drift and diffusion effects, and further characterized the frequency dispersion phenomena associated with the NQS effect. Concurrently, a scalable gate capacitance model was established from the perspective of channel charge distribution. In addition, the scaling rules of parasitic parameters in the equivalent circuit model were presented. For model validation, 12 CMOS transistors with varying geometries were designed and fabricated in a partially depleted silicon-on-insulator (PDSOI) process. Subsequently, ultrawideband scattering (S -) parameter measurements were performed on these devices across the frequency range from 0.2 to 320 GHz. By comparing the model calculation results with the measured data, the maximum root-mean-square error of the model was 0.074. Furthermore, the proposed model was verified to have scaling capability across three geometric dimensions: gate length (L), single-finger gate width (Wf), and the number of gate fingers (Nf). This scalable model provides accurate modeling support for high-frequency circuit design.Pubblicazioni consigliate
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