JFET-input ultra-low noise amplifier for low-frequency noise measurements

Low-frequency noise measurements are essential for the characterization of electronic devices, sensors, and materials, as they provide insight into physical mechanisms, device quality, and long-term stability. The accuracy of such measurements is fundamentally limited by the noise performance of the front-end instrumentation. We propose a topology for the realization of JFET-input voltage amplifiers that allows to obtain equivalent input voltage noise levels lower than 3 nV/√Hz at 100 mHz and below 1 nV/√Hz at frequencies above 1 Hz. The proposed design allows for the dc connection of a biased device under test to the amplifier input without the need for an input ac coupling filter that may result in a reduction of the input impedance, introduction of excess noise, and very long transients. The rejection of the dc component across the device under test, with a bandpass extending down below 100 mHz, is obtained by resorting to internal filters with low-resistance values and supercapacitors, which are characterized by intrinsically low noise. Tests were performed on a prototype employing the IF3602 discrete JFET pair by InterFET. However, other JFETs can be used since, as discussed in this work, the proposed topology allows to easily tailor specific performance parameters, such as different compromises in terms of dc input range, required low-frequency noise level and overall bandwidth. Experimental results demonstrate state-of-the-art noise performance. A comparison with amplifiers reported in the literature shows that, to the best of the authors’ knowledge, the proposed solution achieves the lowest background noise reported for JFET-input amplifiers in the frequency range below 10 Hz.